Here we create a floating point processor that interfaces instructions to memory directly which allows high utilization of the floating point alu.
Processor and its software in VHDL part 4 : memory to memory floating point processing Read More »
Here we will design a pipelined floating point processor, which automatically adapts both the software and the processing pipeline with the floating point module configuration.
Processor and its software in VHDL part 3 : Configurable Processor Pipelining Read More »
Here we make floating point more easily useable with VHDL and FPGA designs by designing a configurable processor that allows us to run many calculations through a single set of floating point hardware in FPGA
Processor and its software in VHDL part 2 : Configurable Floating point processing Read More »
We will design a processor and the software it runs in vhdl. We create the software by inferring intial ram contents with functions that convert instructions to a bit vector arrays.
Processor and its sofware in VHDL part 1 : assembly design Read More »
We design and implement in VHDL a pixel image plotter that allows the creation of a plot from a vector of measurements.
Pixel image from vhdl part 1 : image creation Read More »
In this post we implement wiht VHDL a cascaded second order filter in fixed point which reuses a single DSP block for all of the multiplications.
Fixed point filter with a single DSP block using VHDL records and subroutines Read More »
In this post we design and implement a 6th order Chebyshev filter using fixed point and use it with Efinix Titanium to demodulate a sigma delta bit stream.
Fixed point arithmetic with high level VHDL Read More »
Floating point alu designed in synthesizable VHDL
High level Floating Point ALU in synthesizable VHDL Read More »
Floating point arithmetic in VHDL
Floating Point arithmetic in High Level VHDL Read More »
In this post we discuss how we can allow changes in shared code by abstraction of interfaces in VHDL. In my previous post about object oriented design in VHDL I argued that designing for code reuse is the single most important design goal in code development. Systematic code reuse allows us to continuously increase the
Dependency management in shared VHDL code Read More »
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