VHDL Archives - Page 3 of 3 - Hardware Descriptions

Bandpass and Band stop Filtering with VHDL

Leave a Comment / bandpass and bandstop IIR filtering, Digital Signal Processing, IIR filtering, VHDL / johonkanen

get the VHDL sources https://github.com/johonkanen/ac_inout_psu/tree/bandpass_filter To minimize code rewriting and maximize reuse, object oriented programming languages use inheritance to add existing module features to new modules. This type of code is much easier to reuse as parts of further modules. In VHDL inheritance like code structure can be achieved by instantiating components inside components and […]

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Math : be fruitful and multiply

1 Comment / Digital Signal Processing, IIR filtering, Integer arithmetic, Multiplication, VHDL / johonkanen

get the VHDL sources ac_inout_psusourcemath_librarymultiplier https://github.com/johonkanen/ac_inout_psu/tree/bandpass_filter The power supply is an embedded system which uses measurements from different voltages and currents to control the operation of the power supply. Control algorithms as well as measurements use signal processing to filter out unwanted noise from the analog to digital converter results and control outputs. Function approximations

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Abstract UART in VHDL

Leave a Comment / UART, VHDL / johonkanen

https://github.com/johonkanen/ac_inout_psu/releases/tag/abstract_uart Compile the code with quartus_sh -t <path_to_project_root>cyclone_10tclbuild_project.tcl As with most things, everything usually starts with communication. Since many types of information need to be communicated out of the overall design the the uart is the perfect first design unit to be brought into any project. Uart in this case is also used as an

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AC Power supply code architecture

Leave a Comment / VHDL, VHDL source architecture / johonkanen

In any language, abstraction used for separating of system behavioural description from its level implementation. The code architecture of the power supply shown above is build so that a higher level module instantiates lower level modules and wraps the lower level module interface from any modules higher in the hierarchy. The way this is achieved

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