Building computer console software for UART
datalogging and monitoring
As of right now the bulk of the project is being debugged using 2 console softwares shown below. Git version 861ebf3fb7 of the code is used.
Figure 1. Minimal uart program for receiving data streams from FPGA
Figure 2. Monitor used for ethernet communication logging
The sources are now in the github repository under ac_inout_psu/computer_test_programs/
Build steps for FPGA
The fpga build is very straight forward if the cyclone 10lp evaluation kit is used and quartus_sh is found on path, then create a compile directory and type in the console
quartus_sh -t <path_to>ac_inout\cyclone_10\tcl\build_for_evm.tcl
This will create a project and build it. This should take approximately a minute. After the build is complete, the fpga ram can be programmed with
quartus_pgm -c “Cyclone 10 LP Evaluation Kit [USB-1]” -m JTAG -o “p;./output/top.sof”
Note that the name of the evaluation kit can be obtained by console command
quartus_pgm -l
This should take a few seconds and then the evaluation kit is ready.
Uart Communication
The connection with uart to the evaluation kit is shown below. The two wires taped together and connected to the header are the RX(brown) and TX(black) pins and the orange is the ground. The pin mapping is found in \ac_inout_psu\cyclone_10\tcl\evaluation_kit_pin_map.tcl
The uart to usb converter used is a standard HL2232 FTDI chip which in this case is on a Texas instruments C2000 evaluation kit. The TI kit is not used otherwise, just the uart is needed and thus any comparable usb to uart converter should suffice.
Figure 3. Uart connection with evaluation kit
Both console applications are build using free version of Visual Studio 2019.
Building Uart stream receiver
The uart receiver can be built with Visual studio by creating an empty C++ project
Figure 4. Create empty project with visual studio
After creation just add all three sources. At this point the program will not yet build, first the unicode character set needs to be changed to multibyte character set. Right click on the project name, in this case uart_data_receiver and go to advanced, then change Character set from unicode to multibyte.
Figure 5. add all uart stream receiver sources
Figure 6 property pages
Figure 7. change to from unicode to multi-byte character set
At this point it should build, however the correct comport needs to be used for the software to function properly.
The correct comport is visible in the device manager after the usb to uart device is connected. In my case this is COM4
Figure 8. get com port from device manager
The com port is written in the serial_comm.cpp at line 140 and that is indeed the correct amount of dashes for the com port (:
HANDLE init_serial(void)
{
HANDLE hSerial;
hSerial = CreateFile( "\\\\.\\COM4",
GENERIC_READ | GENERIC_WRITE,
0,
0,
OPEN_EXISTING,
FILE_ATTRIBUTE_NORMAL,
0);
if(hSerial==INVALID_HANDLE_VALUE)
{
if(GetLastError()==ERROR_FILE_NOT_FOUND)
{
printf("does not compute\n");
}
//some other error occurred. Inform user.
printf("does not compute either :(\n");
}
If everything is fine, then building the code should bring up a console with press ‘q’ to quit message
Type in “raw 17” then enter and then “log” and enter and there should be a message for data collection to be started and after a few seconds there should be a message for File saved. This is seen in Figure 1.
The code creates a ad_test.txt file on the projects folder. This can be found on the visual studio projects root folder along with the .vcxproj files. The .txt file in question has two columns of number as seen in Figure 10.
If these are plotted with for example matlab with the readad.m that is also in the repository, then one column presents a garbled messy data and the other should now have a ringing waveform
The reason for this is that one dataset is captured with bytes out of phase, meaning that the 16 bit data is written into the file with preceding packets low 8bit data combined with high bits from the newest packet. FPGA is actually continuously streaming out the data from uart at 100kHz and since no protocol is used and since uart is 8 bits or one byte and the data word consists of 2 bytes, there is no way to capture the data phased correctly every time. The uart receiver code buffers a word and prints out the data with both phases so that one of the data columns is always bad and one is always good. It is very hacky but it is using the absolute maximum data rate possible from the uart. At least a data stream of 16 bit words transmitted at 150kHz is possible to capture using this hacky uart stream.
Figure 9. ad_test.txt as created by the stream receiver software
Figure 10. matlab plot of the ad_test.txt
Uart monitor program used for printing ethernet bytes.
The monitor in Figure 2 uses curses library for managing colors and placement of the console print. Installing curses for visual studio is relatively easy with visual studio package manager.
Other than the curses library the build steps are similar as for the uart stream capture program. Create empty program, then add all sources from under the ac_inout_psu/computer_test_programs/monitor/ , change from unicode to multibyte, check for correct com port and build.
The monitor does not have a way to transmit data to the FPGA, thus if the uart stream was used before, then either reload the stream console and type “raw 3” and enter (or any other number not in the range from 10-17) or just reload the code to FPGA with the quartus_pgm console command. There is no separate VHDL code for the ethernet, so it is just a matter of transmitting the correct data out of the FPGA.
If everything is successful then the console should pop up and print out 256 bytes from ethernet receiver ram followed by MDIO registers on lines 0x80 – 0x9f.
A string of 0xEE means that the receiver has successfully checked the frame check sequence.