Object oriented design in synthesizable VHDL
object oriented design with synthesizable vhdl
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VHDL
Sine and Cosine in Synthesizable VHDL
Sine and cosine are among tthe most fundamental operations and here the functions are implemented in VHDL for FPGA.
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Conquer the Divide
The next most important operation after summation, subtraction and multiplication is the fourth fundamental operation, division. As the inverse operation for multiplication, division is used for calculating scaling gains for measurements and controls. It is also needed for calculating further mathematic functions, for example arctangents are readily calculated using rational approximations which require evaluation of division
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Real-Time dynamic simulation with FPGA vol 2 : Differential equations on a chip
Sources are found under the Github link at ac_inout_psu/source/math_library/ In part 1, a general purpose state variable object was designed and it was used to build a LC filter model. Now the designed modelling tools are used for the entire power supply model seen in Figure 1. The designed model is then coded in VHDL
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Real-Time dynamic simulation with FPGA vol 1 : the space of states
Complete sources can be found on the projects github repository from ac_inout_psu/source/math_library/. The FPGA test code is written in /ac_inout_psu/source/system_control/system_components/system_components.vhd Now with the ethernet communication established, next goal is to develop the power electronics control and protections. This is done against a hardware simulation model for the power electronics. The simulation takes in the modulator
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Ethernet vol 4 : TXing
Complete sources from github are found at /ac_inout_psu/source/system_control/system_components/ethernet_communication/ethernet/ethernet_frame_transmitter/ So far the journey to ethernet has gone though the physical cable status monitoring with MDIO, frame capturing through RGMII and In the previous blog post, a minimal protocol stack for UDP header parsing designed and it was verified against ethernet connection with a computer. The working
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Gigabit ethernet vol 3: processing protocols from Reasonably Accessible Memory
See the most current sources in the Github repository at ac_inout_psu/source/system_control/system_components/ethernet/ Memory sources are in -/ethernet/common/dual_port_ethernet_ram/ With the gigabit physical layer receiver completed, next task is to create minimal set of rules, or protocols for connecting the FPGA with the ethernet to a computer network. With most computer operating systems, ethernet is implemented as part
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Ethernet vol2 : a look to the RGMII-connection
Get complete sources from ac_inout_psu/source/system_control/system_components/ethernet/ Now with the link up and running, as indicated by the data accessed through the MDIO, the next thing to do is to catch the ethernet frame from the ethernet cable through phy RGMII connection. RGMII is a 12 io source synchronous interface consisting of separate RX and TX clock
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Gigabit Ethernet vol1 : MDIO and communications wonderland
Get the complete sources after cloning github repository from ac_inout_psusourcesystem_controlsystem_componentsethernetmdio_driver Gigabit Ethernet is probably the most convenient way to communicate with an embedded system. The link is full duplex, extremely robust even through ridiculously long cables and the cable is even galvanically isolated from both ends. The ethernet port is available on all PC hardware
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