In this post we discuss how we can allow changes in shared code by abstraction of interfaces in VHDL. In my previous post about object oriented design in VHDL I argued that designing for code reuse is the single most important design goal in code development. Systematic code reuse allows us to continuously increase the […]
Dependency management in shared VHDL code Read More »
object oriented design with synthesizable vhdl
Object oriented design in synthesizable VHDL Read More »
Sine and cosine are among tthe most fundamental operations and here the functions are implemented in VHDL for FPGA.
Sine and Cosine in Synthesizable VHDL Read More »
The next most important operation after summation, subtraction and multiplication is the fourth fundamental operation, division. As the inverse operation for multiplication, division is used for calculating scaling gains for measurements and controls. It is also needed for calculating further mathematic functions, for example arctangents are readily calculated using rational approximations which require evaluation of division
Conquer the Divide Read More »
Sources are found under the Github link at ac_inout_psu/source/math_library/ In part 1, a general purpose state variable object was designed and it was used to build a LC filter model. Now the designed modelling tools are used for the entire power supply model seen in Figure 1. The designed model is then coded in VHDL
Real-Time dynamic simulation with FPGA vol 2 : Differential equations on a chip Read More »
Complete sources can be found on the projects github repository from ac_inout_psu/source/math_library/. The FPGA test code is written in /ac_inout_psu/source/system_control/system_components/system_components.vhd Now with the ethernet communication established, next goal is to develop the power electronics control and protections. This is done against a hardware simulation model for the power electronics. The simulation takes in the modulator
Real-Time dynamic simulation with FPGA vol 1 : the space of states Read More »
Complete sources from github are found at /ac_inout_psu/source/system_control/system_components/ethernet_communication/ethernet/ethernet_frame_transmitter/ So far the journey to ethernet has gone though the physical cable status monitoring with MDIO, frame capturing through RGMII and In the previous blog post, a minimal protocol stack for UDP header parsing designed and it was verified against ethernet connection with a computer. The working
Ethernet vol 4 : TXing Read More »
See the most current sources in the Github repository at ac_inout_psu/source/system_control/system_components/ethernet/ Memory sources are in -/ethernet/common/dual_port_ethernet_ram/ With the gigabit physical layer receiver completed, next task is to create minimal set of rules, or protocols for connecting the FPGA with the ethernet to a computer network. With most computer operating systems, ethernet is implemented as part
Gigabit ethernet vol 3: processing protocols from Reasonably Accessible Memory Read More »
Get complete sources from ac_inout_psu/source/system_control/system_components/ethernet/ Now with the link up and running, as indicated by the data accessed through the MDIO, the next thing to do is to catch the ethernet frame from the ethernet cable through phy RGMII connection. RGMII is a 12 io source synchronous interface consisting of separate RX and TX clock
Ethernet vol2 : a look to the RGMII-connection Read More »
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