FPGA RAM control

See the most current sources in the Github repository at ac_inout_psu/source/system_control/system_components/ethernet/ Memory sources are in -/ethernet/common/dual_port_ethernet_ram/ With the gigabit physical layer receiver completed, next task is to create minimal set of rules, or protocols for connecting the FPGA with the ethernet to a computer network. With most computer operating systems, ethernet is implemented as part […]