hardware descriptions

RGMII

Ethernet vol 4 : TXing

1 Comment / Ethernet, FIFO control, RGMII, VHDL /

Complete sources from github are found at /ac_inout_psu/source/system_control/system_components/ethernet_communication/ethernet/ethernet_frame_transmitter/ So far the journey to ethernet has gone though the physical cable status monitoring with MDIO, frame capturing through RGMII and In the previous blog post, a minimal protocol stack for UDP header parsing designed and it was verified against ethernet connection with a computer. The working […]

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Ethernet vol2 : a look to the RGMII-connection

Leave a Comment / Ethernet, RGMII, VHDL /

Get complete sources from ac_inout_psu/source/system_control/system_components/ethernet/ Now with the link up and running, as indicated by the data accessed through the MDIO, the next thing to do is to catch the ethernet frame from the ethernet cable through phy RGMII connection. RGMII is a 12 io source synchronous interface consisting of separate RX and TX clock

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